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SEM-based Nano-probing

Technical Concept

The need for high-performance computing is driving advanced manufacturing processes gradually towards the post Moore’s era. Process nodes are shrinking. Processes have reached the 5nm level and are expected to reach the extreme 3nm and 2nm levels in the near future. Moreover, transistors are evolving from the previous planer structure to the 3D FinFET and GAA structures. These changes have refreshed existing processes.

 

As processes continue to be scaled down, the old AFM-based nano-probing technology for measuring single device can no longer keep up. Instead, we must turn to SEM-based nano-probing technology in order to confirm the morphology of advanced process samples and perform the subsequent electrical measurement analysis.

 

The SEM environment allows for clear, microscopic observations of the surface topography of nano-scale transistors via low-accelerating voltage analysis. It also enables electrical measurement and accurately locates the points of failure, which can be used to deduce the failure mode of a device. The electron beam, with its low accelerating voltage, can also avoid contaminating the sample’s surface or causing the drift of transistor characteristics. The nP4 combines the following functions and advantages and provides more analysis options for advanced process products. At present, the smallest process technology that can be successfully measured is the 5nm FinFET. Each function is described in detail below:

 

 

1.I-V Curve Measurement

Nano-probes provide a non-destructive form of electrical measurement for devices. It is used mainly to confirm the device’s characteristics curve and leakage path in order to increase the success rate when searching for defects while avoiding running into the problem of having a damaged sample that cannot be further analyzed. The probe can have better contact with the target when used in conjunction with SEM observation because the electrical measurement environment will be more stable.

 

Furthermore, its operating voltage can be as low as 100eV. As such, it can effectively avoid the problem of electrical drifts caused by the accumulation of charges in the test piece. For example, a 7nm device operates at an accelerating voltage of 1KeV. Its electrical behavior is significantly different at lower accelerating voltages. For analysis engineers, this can lead to misjudgments.

 

 

Figure 1. Operation of 7nm devices at different accelerating voltages; Its accelerating voltage can be as low as 100eV

 

 

2.Thermal Stage

As processes become more advanced, products too are changing. The popularization of advanced products means that they have to endure more severe use environments, from the high temperatures that come with high operating power to the low temperatures faced when operating at high altitudes. As such, the nP4 is equipped with an additional temperature control stage that allows for the electrical analysis of samples under different ambient temperatures. This feature is an excellent analytical tool for device and circuit design engineers.

* The machine’s adjustable temperature range: -40~150℃

 

 

 

Figure 2. Device temperature rise and fall measurement procedure

 

 

3.EBIC Analysis

 

 

4.EBAC Analysis

 

 

5.EBIRCH Analysis

 

 

6.750ps pulsed IV

Typically, when making IV measurements, the voltage sweep is conducted in a step by step rise. This means that the voltage is held constant at each voltage set point for a period of time before it moves on to the next voltage set point. However, pulsed IV function is only by using a pulse at each voltage set point, which resistance and capacitance effects (RC effects) can be measured. The parameter analyzers on the market usually come equipped with this function. The nP4 is also equipped with this function. Furthermore, its cycle can be as short as 750ps. This makes it an excellent tool for studying the delay effect.

 

By supplying the gate pulse voltage or current, transient waveforms can be generated with transistor switches. In this way, it is possible to determine the delay time in the voltage’s rise and fall when the transistor is switched on and off. We can then compare the waveforms of normal and failed products to determine whether the gate connection is abnormal and detect whether there is leakage in the gate oxide layer.

 

 

Figure 3. The high speed pulsed IV measurement function detects device time delays due to parasitic resistance or capacitance issues

 

 

7.C-V Measurement

C-V is used mainly for measuring the characteristics of MOS capacitive components. The application of a voltage to the device indirectly affects the charge changes in the dielectric layer between the metal layers and the gate oxide layer. By measuring the capacitance of normal and failed products, it is possible to calculate the thickness of the insulating layer and judge its quality.

 

 

Figure 4. Infer device channel problems by comparing device ID-VG characteristics then verify using TEM

 

 

 

Equipment

nProber IV - 4th Generation SEM Based NanoProber

 

 

 

FAQs

Q1.Will measuring the I-V Curve under an SEM environment affect the electrical performance?

A:When using the probe in a Low kV environment, the scanning electron beam is turned off once the probe locates the target to prevent the electrical properties of the sample from being influenced by excess electrons during the measurement of the I-V curve.

 

 

Q2.Under what conditions can an EBIRCH be executed?

A:The EBIRCH mainly detects short and high impedance defects.

  • EBIRCH:short or high impedance defects exist between the metal layers and poly/contact layers
  • EBIC:There is leakage in the GOX/Junction (Poly/Contact layer)
  • EBAC:There is an Open or High Impedance phenomenon between the metal layers

 

 

Q3.How do you find the real cause of gate oxide breakdowns?

A:You can easily locate gate oxide breakdowns using EBIC technology! Electron-hole pairs are generated when the electron beam hits the sample. Then the path created by the probe allows a current to form. This enables the use of a current image to determine the location of the defect.

 

 

 

Contact

Taiwan Lab

Mr. Tzou

: +886-3-6116678 ext:3917

: +886- - - - - - -

jb_pfib@ma-tek.com

Shanghai Lab

EFA team

: +86-21-5079-3616 ext:7051

: 135-2431-3161

: efa_sh@ma-tek.com