After 2000, the dimension of gates have continually shrunk from 0.13 um to 90 nm, 65 nm, 45 nm, 32 nm, and then even smaller, and the material for metal wire has changed from Al to Cu. These can improve the performance of the chip.
For smaller technology nodes, such as 28 nm and 20 nm, new gate dielectric material, high-k metal, replaced the traditional poly-Si and metal salicide in order to gain better electric performance. Such high-k metal gate is a multi-layer structure with different compositions. The thickness for each layer is around 1-2 nm. Therefore, it is a task to determine its thickness, interface flatness, and composition by current tools.Besides, the structure of the field transistor has changed from 2D to 3D in order to control the leakage level and enlarge the turn on current.
The figure below exhibits structural analysis on two ICs with 22 nm and 40 nm technology nodes purchased from the market, where traditional planar HKMG and FinFET are clearly shown.
Cross-section TEM image of IC purchased from the market.
(a) 40 nm planar HKMG
(b) EDX line scan along the transistor
(c) Cross-section TEM image of BEOL and dielectric layers
(d) EDX line scan along the BEOL and dielectric layers
(e) Cross-section TEM image of FinFET.