Dynamic random access memory, DRAM, is one of memories in PC. The demand for memory is quite high not only for the software execution but also for data storage. Because the electron charge decays with time, stored data needed to be rewritten, repeatedly. The data will disappear after switching the power off. So DRAM is a volatility memory and data is stored in the capacitance.
There are several key issues about DRAM fabrication technology：
- How to lower the electron charge decay in the capacitance
- How to enlarge the capacitance with decreasing the base area
- How to etch high aspect ratio trench and covered with dielectric and metallic layers
The figure below the latest advanced fabrication technology for DRAM is demonstrated, where the line width for the word line is 36 nm. The traditional planar gate design has been replaced by the recessed gate design. Therefore, it becomes crucial to aptly control the thickness of nano trench and dielectric layer during etching.
TEM image of Samsung DRAM purchased from the market.
(a) Cross-section image
(b) The layout of the planar structure
(c) Cross-section image along the word line
(d) Cross-section image along the bit line, where recessed gate can be clearly observed.
The following figure is the component determination analysis in the dielectric materials at capacitance structure for a DRAM product. With help of TEM/EDX, dielectric thin layers of ZrO2-Al2O3-ZrO2 can be clearly identified between SiGe/TiN and TiN, the two electrodes of capacitance. Although the thickness of ZrO2-Al2O3-ZrO2 is 2.6 nm, 1.4 nm, and 6.4 nm, respectively, still, ZrO2-Al2O3-ZrO2 can be detected by TEM/EDX.
(a) ZrO2 - Al2O3 - ZrO2 dielectric layer in DRAM capacitance
(b) ZrO2 - Al2O3 - ZrO2 dielectric layer can be analyzed by TEM/EDX.