IC產業應用方案

DRAM

Samsung 512Mb C-die DDR SDRAM Constructional Analysis
This report contains a microstructural analysis of the memory cell and peripheral circuits. Plan-view (P-V) and cross-sectional (X-S) SEM, TEM were conducted to reveal the circuit layout and material architecture of the devices. SIMS (Secondary Ion Mass Spectrometry) was used to determine the doping profiles of device formation. The report also contains the package and die photographs, showing the segments of cell array, word line decoder, sense amplifier, I/O circuits, and peripheral circuits.
Gate in memory cell array
圖-1

1-1. List of Figures

  • 0.1.1 Package marking & photograph
  • 0.1.2 Package X-ray photograph & pin configuration
  • 0.1.3 Die Marking & Photograph
  • 0.2.0 Memory array structure illustration (P-V)
  • 1.0.0 X-S through word line (TEM)
  • 1.0.1 Metal 1 X-S through word line (TEM)
  • 1.0.2 Metal 2 X-S through word line (TEM)
  • 1.0.3 P-1 X-S through word line (TEM)
  • 1.0.4 P-1 and STI dimension measurement - X-S through word line (TEM)
  • 1.0.5 Gate oxide thickness measurement - X-S through word line (TEM)
  • 1.1.0 X-S through bit line (TEM)
  • 1.1.1 Metal X-S through bit line (TEM)
  • 1.1.2 Capacitor X-S through bit line (TEM)
  • 1.1.3 Bit line and capacitor bottom X-S (TEM)
  • 1.2.1 Periphery circuits structure – X-S through word line (TEM)
  • 1.2.2 Periphery circuits structure – X-S through word line (TEM)
  • 1.2.3 Periphery circuit structure – X-S in parallel with word line (TEM)
  • 1.2.4 Periphery structure – X-S in parallel with word line (TEM)
  • 1.2.5 Periphery metal X-S in parallel word line (TEM)
  • 1.2.6 Periphery structure X-S in parallel word line (TEM)
  • 2.0.1 Word line and bit line  material (TEM/EDX)

1-2. List of Figures

  • 3.0.1 Memory array delayered to expose capacitor top (SEM)
  • 3.0.2 Memory array delayered to expose capacitor (SEM)
  • 3.0.3 Memory array delayered to expose node contact (SEM)
  • 3.0.4 Memory array delayered to expose bit line contact (SEM)
  • 3.0.5 Memory array delayered to expose word line (SEM)
  • 3.0.6 Memory array delayered to expose substrate (TEM)
  • 3.0.7 Periphery active area (TEM)
  • 4.0.1 Doping profile in memory cell array (SIMS)

2. Device Summary

Part Identification

  • Manufacturer:Samsung
  • Part Number:K4H510838C-UCCC
  • Type:DDR SDRAM
  • Configuration:64M x 8
  • Die Marking:SAMSUNG K4H510838C-CXX
  • Date Code:525
  • Package:66-pin TSOP II

Die/Cell Measurement

  • Die size:7.40 mm x 8.43 mm
  • Cell size:0.072um

Process

  • Type:CMOS
  • Metal Layers:2
  • Poly Layers:2
  • Word Line Materials:WSix
  • Bit Line Material:W
  • Minimum Feature Size:0.055um (P-1)
  • Line/Space:1/2.5

Periphery Feature Sizes

  • Contact Size:0.14um
  • Min. Poly Width:0.095um
  • Min. M1 Pitch/Width:0.48um/0.24um
  • Min. M2 Pitch/Width:0.81um/0.51um

3. Memory Cell Structure

圖-2
Memory Cell Structure

4. Memory Cell Design Rule

1. AA (active area) – AA 0.18 μm in width, 0.49 μm in length; AA-AA min. distance 0.11 μm
2. WL - line width (channel length) 0.06 μm, line spacing 0.14 μm , pitch 0.2 μm;
3. BL contact – contact size 0.06 μm in diameter;
4. Node contact formation –contact size 0.06 μm
5. BL formation –line width 0.08 μm, line spacing 0.1 μm, pitch 0.18 μm;
6. Capacitor – capacitor size 0.2 μm in diameter;
7. Metal-1 – line width 0.45 μm, line spacing 0.33 μm, pitch 0.78 μm;
8. Metal-2/Metal-1 via – via size 0.24 μm in diameter;
9. Metal-2 - line width 0.41 μm, line spacing 0.28 m, pitch 0.69 μm.

5. Periphery Layout Design Rule

1. AA (active area) – 0.14 μm in width, AA-AA min. distance 0.13 μm;
2. Gate length  0.095 μm,
3. Metal-1 contact  – contact to poly-Si 0.14 μm in diameter, contact to AA 0.14 μm in diameter;
4. Metal-1 – line width 0.24 μm, line spacing 0.24 μm, pitch 0.48 μm;
5. Metal-2/Metal-1 via – via size 0.23 μm in diameter;
6. Metal-2 - line width 0.51 μm, line spacing 0.3 μm, pitch 0.81 μm.

6. Summary of Critical Dimension Measurement

圖-3
Summary

7. Reference

1. J.Y.Kim et al., Symp. on VLSI Tech, pp. 34-35, 2005
2. O.J.Oh et al., Proceedings of ESSDERC, Grenoble, France, pp. 177-180, 2005
3. J.Y. Kim et al., IEEE, pp. 33-34, 2005

0.1.1 Package marking & photograph

圖-4 (a) Package markings: SAMSUNG 525 K4H510838C-UCCC H5L 8 CMEL75BB (Before Decapsulation)
(b) Lead On Chip (LOC) technology was used in this product. (After Decapsulation)

0.1.2 Package X-ray photograph & pin configuration

圖-5
Package X-ray

0.1.3 Die marking & photograph

圖-6 (a) The chip size was estimated to be 8.43 mm x 7.40 mm
(b)Chip logo:SAMSUNG K4H510838C-CXX

1.1.0 Cross section through bit line (AA', TEM)

圖-7
AA', TEM
  • 2M4P
  • Stacked cylindrical capacitors
  • Capacitor over bit line structure

1.0.3 Poly-1 cross section through word line (AA', TEM)

圖-8

1.0.4 Poly-1 and STI dimension measurement-cross section through word line(TEM)

圖-9

1.0.5 Gate oxide thickness measurement – cross section through word line (TEM)

圖-10 Minimum gate oxide thickness = 61Å

Minimum gate oxide thickness

1.2.1 Periphery circuits structure – cross section through word line (TEM)

Poly 2 (blanket tungsten) was employed as local inter-connects in periphery circuits.

圖-11
TEM

1.2.3 Periphery circuit structure - cross-sectional in parallel with word line (TEM)

圖-12
Periphery circuit structure

1.2.6 Periphery structure cross section in parallel word line (TEM)

圖-13
Periphery structure cross

3.0.6 Memory array delayered to expose substrate (TEM)

圖-14

3.0.7 Memory array delayered to expose substrate (TEM)

圖-15

4.0.1 Doping profile in memory cell array (SIMS)

The P-well depth is estimated as 1um. The deep N-well is estimated as 2um.

圖-16
Doping profile