ESD Testing & Design Service
Technical Concept
MA-tek provides various ESD services such as HBM, MM, socket CDM, non-socket CDM, latch-up and TLP testing service. The facilities can support both room-temperature and high-temperature testing modes. We provide different types of BGA sockets for ESD/Latch-up testing. Furthermore, we offer packaging services (Au/Al wire bonding, die mount, epoxy, encapsulation), COB and package level tests, system level testing of module, mother board, and electronic system by ESD gun.
Human Body Model (HBM)
It is relatively easy to generate considerable charge and potential, by walking on carpeting or hard floors. When a charged person touched a conductive path of an IC package or circuit board, the body charge is either shared with the device or discharges through the device to ground. (Figure 1) The discharge is rapid, in a few hundreds nano-seconds (ns), and is frequently causing damage or failure of the device.
Above picture, HBM ESD event :
a charged person touched a conductive path of an IC package, the body charge is either shared with the device or discharges through the device to ground.
The most frequently used test standards for HBM include: MIL-STD-883G method 3015.7, EIA/JEDEC JESD22-A114E, ESDA STM5.1-2001. HBM is modeled by a 100pF capacitor discharged through a switching component and 1,500 ohm series resistor into the component. (picture below)
| Human Body Model (HBM) equivalent circuit |
Machine Model
Machine Model (MM) is proposed for automated assembly and manufacturing environment. When a machine with accumulated charges touched a conductive path of an IC package or circuit board, the charges are either shared with the device or discharges through the device to ground.
The most frequently used test standards for MM include: EIA/JEDEC JESD22-A115A and ESDA STM5.2-1999.
MM is modeled by a 200pF capacitor discharged directly into a component with no series resistor. (picture below). The discharge occurs from a few to tens of ns during which the current levels can reach several amperes.
| Machine Model (MM) equivalent circuit |
Charged Device Model
IC components can be charged in various ways. If the component touches a metallic surface while it is charged, a very rapid discharge occurs in a few ns during which the current levels can reach several tens of amperes. Possible ways that IC components are charged and discharge are shown in Figure 4(a) and 4(b).
Figure(a) Devices are frequently charged by sliding down a delivery rail to a tester, automated insertion machine, or in marking and branding equipment. If the component touches a metallic surface while it is charged, a very rapid discharge occurs.
Figure(b) Device is charged by sliding down a delivery rail. If tweezers touches a pin of the charged device, a very rapid discharge occurs. Several methods have been explored to duplicate the real-world CDM event and provide a suitable test method that duplicates the types of failure that have been observed in CDM caused field failures. Current procedures use two different CDM test methods. One is termed CDM (non-socket CDM) which uses either direct or field induced methods to apply to the DUT (device under test). The other addresses devices that are inserted in a socket and then charged and discharged in the socket. It is named the socketed discharge model (SDM).
The most frequently used test standards for CDM (non-socket CDM) include: EIA/JEDEC JESD22-C101C and ESDA STM5.3.1-1999. This procedure for SDM is still a work in process and has had to overcome a number of limitations including too great a dependency on the specific design of the SDM tester. A draft document, DSP5.3.2-2003 Draft, was published in 2003.
The equivalent circuit of CDM is shown in picture below :
| Charged Device Model equivalent circuit |
System- Level ESD test with IEC-61000-4-2 test standard
This international standard defined by IEC (International Electrotechnical Commission) relates to the immunity requirements and test methods for electrical and electronic equipment subjected to static electricity discharges, from operators directly, and to adjacent object. In addition, it includes electrostatic discharges which may occur from personnel to objects near vital equipment.
Simplified diagram of the ESD generator in IEC-61000-4-2
The test can be performed in the following manner:
(a) Air Discharge Method: Air discharge at insulating surfaces of the EUT (equipment under test). The charged electrode of the test generator is brought close to the EUT, and the discharge actuated by a spark to the EUT.
(b) Contact Discharge method: Contact discharge to the conductive surfaces of the EUT. The electrode of the test generator is held in contact with the EUT, and the discharge actuated by the discharge switch within the generator.
(c) Discharge to Horizontal Coupling Plane (HCP) and Vertical Coupling Plane (VCP): Discharges to objects placed or installed near the EUT are simulated by applying the discharges of the ESD generator to a coupling plane, in the contact discharge mode.
Transmission Line Pulse (TLP)
- In-depth characterization of current conduction and voltage within ESD protection structures under influence of ESD events.
- Getting the ESD design right at the first time and shortening the product development time.
- Reproducing failure mechanism and electrical behavior of a device in response to a HBM ESD pulse.
Package Level TLP Testing
Wafer Level TLP Testing
Equipment CapacityThermo KeyTek Zapmaster tester, 256 pins
Thermo KeyTek Mk-2 tester, 768 pins
Oryx Orion Non-socket CDM tester
High temperature Latch-up test module: THERMONICS / T-2600BV Figure D
ESD Gun system: NoiseKen / ESS-2000 Figure E
TLP Tester (Celestron)
Application / Service Item
(I)ESD Testing [Testing standards]
According to different Electrostatic Discharge (ESD) model, three kinds of component ESD testing standards (HBM, MM, and CDM) and one system testing model (HBM) are used to verify the reliability concern of component and system, respectively. ma-tek testing facilities can support up to 768 high pin counts of a single device or even more pin counts with pin rotation design. Failure criteria of ESD test is judged by I-V shift for more than 30% or direct I-V short. ESD testing results will be reconfirmed by self-developed intelligent Recognition Software. The testing system is also equipped with Report Auto-Generation Software. The testing quality is guaranteed.。
MA-tek provides：
- HBM、MM、SCDM (socketed CDM)、CDM (non-socketed)
- System-level ESD testing (ESD gun)
(II)Latch-up Testing [Testing standards]
The latch-up testing is used to evaluate the noise or transient immunity of the CMOS ICs. Latch-up is a parasitic circuit effect due to the p-n-p-n four-layer thyristor structure in CMOS, Bipolar, BiCMOS devices.
MA-tek provides：
- Room temperature Latch-up testing
- High temperature Latch-up testing
- 768 pins independent digital vector input dynamic Latch-up testing
- Failure Criteria of ESD/Latch-up test
(III)ESD/Latch-up Design Services
In addition to ESD/Latch-up testing services, ma-tek also offers ESD protection I/O cell library, ESD/Latch-up circuit design consulting, and in-depth analysis of customer layout to ensure maximum on-chip ESD robustness and immunity of ESD/Latch-up events.
MA-tek provides a wide range of ESD-related services：
- Customized ESD/Latch-up free IC circuit design from generic concept to circuit layout
- Robust I/O cell libraries
- ESD/Latch-up design rule establishment
- ESD training support and consulting services
- Total solution failure analysis
- Board-level CDM consulting
- System-level ESD consulting
- Class 0, ESD free, manufacturing environment auditing
I/O Cell Libraries
MA-tek work with our strategic partners in ESD design services. The technologies used in I/O cell libraries were mainly developed and patented by ITRI/STC. The technical team is associated with Amazing IC, working closely with NCTU/EE Professor MD Ker.
Characteristics of our I/O cell libraries
- Cell area is very small in order to reduce chip cost.
- With high ESD immunity， the input capacitance of analog input cell is optimized for high bandwidth.
- Whole chip ESD protection scheme with high ESD immunity is provided.
- The mixed-voltage-tolerant (1.8V/3.3V in 0.18-µm CMOS processes， 2.5V/3.3V in 0.13-µm CMOS process) I/O cell libraries with high ESD immunity are provided.
- The I/O cell libraries in high-voltage CMOS process (0.35-µm 18V and 0.25-µm 40V HV process) with high ESD immunity are provided.
Patents of the key to success
- Area-Efficient VDD-to-VSS ESD Protection Circuit， US 5744842, ROC 095463, (1998-2016).
- ESD Protection Circuits for Mixed Mode Integrated Circuits with Separated Power Pins, US 6075686, ROC 109893, 1999-2017).
- Low capacitance Bonding Pad for Semiconductor Device， US 6448641, ROC 131368, (2001-2018).
- ESD Protection for a Mixed-voltage Device Using A Stacked-Transistor-Silicon Controlled Rectifier, US 6747861, ROC 190384, (2003-2022).
Contact Window
Rinie Su
Tel：+886-3-6116678 ext：6903
Mobile：+886-935-200095
Tel：+886-3-6116678 ext：1721
Mobile：+886-952-303813
Technical Consutant:
Benjamin Yeh
Tel：+886-3-6116678 ext：1900
Mobile：+886-922-303819
Email：esd@ma-tek.com
